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May 11, 2005

The 4th IEEE David C. Evans Conference on Computer Engineering Education

This annual computer engineering education conference hosted by BYU each year is really enjoyable. They do an excellent job organizing the conference, and this year is no exception. One of the invited speakers, David Harris or Harvey Mudd, gave a very enjoyable presentation on his new book and the VLSI course built around it. We also enjoyed presentation from Erik Brunvund (University of Utah), Annette Bunker (Utah State University), and Chris Myers (University of Utah). I found Annette's grading system very interesting. Something to consider it graduate courses.

  • David Harris - Harvey Mudd University - CMOS VLSI Design, A Circuits and Systems Perspective.
    • VLSI is appropriate for undergraduates.
    • Preload project schedule to comoplete 2 weeks before semester ends.
    • End semester to with an open ended design project with proposal, design document, and presentation.
    • Sun sponsored clinics produce chip projects for students.
    • One Sun sponsored chip project created a small company to produce chip testers for University classes.
    • Sponsors a 1 hour seminar for freshman that exposes students to digital logic and chip design.
    • Seminar is 1 night a week for 3-4 hours.
    • Purely lab driven with specific projects that lead students to a point where they can do an open ended chip design project.
    • Estimated time is 10 hours preparation with a 5 hour weekly commitment.
    • Soldering taught with CAD flow, basic circuits, etc.
    • How could we do this at BYU? Would need to curb to current trends in CS. C#, etc.
  • Clint Cole - Digilent Inc. - Perspectives on Integrating New Technologies into Engineering Programs
    • Circuit design hardware and software for educations markets.
    • Specialize in demo-boards for designs and educational systems.
    • Good at configurations and software; lots-o-support too for the boards.
    • Not good on high-end design (12 layer boards really break things).
    • Business model is to have every student buy the hardware; guarantees continuous sales; better for business than just stocking up a lab.
    • Arguement is that students with own hardware can work anywhere they want; basic board that is big enough for 8-bit controller is around $60.
    • OEM jobs fund academic development.
    • Want to get things into computer science so students learning algorithms can write algorithms to move robot arms etc.
  • Erik Brunvand - University of Utah - “Add, Multiply, and Divide - How Hard can they Be!?”
    • New course is CS5830
    • Digital Arithmetic book is written more for mathematicians; very formal and exercises somewhat hard.
    • VLSI not a prerequisite for the course; assume gate-level design and CMOS understanding; teach CAD tools and do gate-level or transistor level designs.
    • Project: Basic CAD tool stuff
    • Project: build 2 prefix adders and plot performances for each student design.
    • Project: 16x16 multiplier circuit project (note: this is only transistor design class---no layout).
    • Project: SRT divider circuit (teams of two) with 24-bit arguments and a 12-bit result.This project required a lot of work!
    • Final project: FP unit with one operation using 8-bit exponent with an 11-bit fractional part. No NaN and exceptions. Restrict to only normalized numbers.
    • Optional final projects: interpolator, FP ray-box intersection, NxN array multiplier, FP square root, etc. These are subject to proposal and review by Prof.
    • Projects drove entire grade in class. No homework and exams.
    • Circuits built using University of Utah digital cell library with 25 cells integrated into Cadence flow.
    • Cells can support a mixed-mode simulation (part switch and part analogue) this was essential for testing. Use Verilog to drive circuits using digital test vectors that are fed to analogue model of circuit.
    • Mixed-mode sends Verilog digital signals in to analogue circuit model with another conversion back to digital switch level outputs that can be verified using assertions in the Verilog test harness.
  • Annette Bunker - Utah State University - “Green Code: A First Experience in Teaching Formal Verification”
    • Graduate level course requiring programming, discrete math, and digital design experience.
    • Text: Introduction to Formal Hardware Verification by Thomas Krophf
    • Had to teach basic Automata theory because most students were computer engineering background.
    • One page articulation assignments on topic covered in class.
    • Projects: BDD package, CTL model checker, and theorem proven (base line simple).
    • Final project with proposal, paper, and presentation.
    • Used a grade enhancement grading scheme that provides flexibility to the student--interesting grading scale because student choses what grade they want and then complete the necessary projects to get the grade.
    • There are only 3 levels of grades: pass plus, pass, and fail.
    • Iterate on submissions until required grade is obtained.
    • Provide options and enhancements as requirements to A grades; options obtain a grade and enhancements raise a half grade (i.e., B to B+).
    • Grading system received very positive reviews. Students always knew where they were with respect to their grade.
    • 5 students started but only 3 finished (1 failed and 1 cheated).
    • The articulations really helped improve the writing (1 page writing project) -- requires heavy edit and feedback for writing project -- use a tech editor in English to reduce load or have students read and grade each others papers.
    • Suffered the typical issues related to class: students did not come prepared to class, struggled with programming, did not manage time well, and often misunderstood the material.
    • Ask question on BDD lab: apply or ITE algorithm? Any difference in which is easier to understand/implement for the student?
    • In teaching LTL/CTL, did you struggle to help students see the practical application?
    • Did they implement just checkEG and checkEU for CTL model checker or all operators.
    • How did you teach the variable translation for the preimage calculation on the transition relation for the CTL symbolic lab?
    • Did you use a visualizer for the BDD package? GraphViz?
    • May introduce ML for students; BDDs and MC project were hard to get students into.
    • Need a pass late grade that requires enhancement to get full points. Firm deadline might help.
  • LeRoy Bearnson, Brigham Young University, “Networking for Computer Engineers”
    • This course is dramatically different from the course offered in the computer science department at BYU. Focuses much more on the electrical and communication issues, as well as a lot of time below the network layer.
    • Is it possible to merge the CS network class with the CE network class?
    • The course covers a wide variety of mediums and methods: Wireless, Ethernet, DLS, ATM, Token, etc.
    • Labe: Lan Analyzer/Frame analysis, VLAN configurations, Router/switch programming; specific on configuration of network.
    • There is little or no programming; direct hands-on experience with the actual network hardware: switches, routers, terminals, etc.
  • Chris Myers - University of Utah - “Asynchronous Circuit Design and Its Application to Modeling Biological Systems”

Posted by egm at May 11, 2005 01:33 PM

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