Michael Jones, PhD

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registers and interrupts

• words are 32 bits, halfwords are surprisingly 16 bits and bytes are 8 bits.

Registers

• 31 general purpose 32 bit registers.
• 6 status registers.
• r14 is the link register. which holds a copy of the pc value (r15) during a branch with link instruction.
• r15 holds the pc.
• r13 is, by convention, the stack pointer. 2-8
• each mode can treat some registers differently. fast interrupt mode (fiq) is the most different. Looks like the fiq mode just "reservers" (or banks in arm parlance) 8 registers to speed up data transfer.
• thumb mode has 8 regs (though you can access the higher regs directly in ASM)
• the CPSR is the CCR. Not sure what CPSR stands for. There are also 5 SPSR registers for exception handlers 2-13

exceptions are handled at instruction boundaries and there's tons of detail in 2-16 if you want to read it. Exception priorities on page 2-22 table 2-5

Max interrupt latency in FIQ mode is 29 cycles. Min interrupt latency in FIQ or IRQ modes is 5 processor clock cycles 2-23.

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Timing

page 6-29 has a nice summary of instruction timing. Its nice that there's so few opcodes. Instruction timing depends on the length of a N, S, I and C cycle. These are defining in bus cycle types on page 3-4, well really on page 3-5.

Looks like the various kinds of cycles are how one might access memory. The timing models sort of assume that the DRAM will always give you back your data within a cycle but there's a way to stretch your bus cycles.

Timing of multiplication instructions depends on whether or not the operand contains all 0's or 1's in certain locations.

Don't forget to add in busy-wait loop time for non-instantaneous co-processor accesses.